Functional Constraint Extraction at Register Transfer Level for ATPG to Improve Verification in terms of Coverage

---------------------------------------------------------------------***--------------------------------------------------------------------Abstract The gate level techniques are used in simulation to identify ISE’s and also these techniques are implemented based on Sequential Automatic Test Pattern Generation (ATPG). But now a day’s IC’s are very complex so by using above gate level method, it is very difficult to compute and also in this process, illegal states are occur but this causes unwanted behavior and false error detection in the verification process. To overcome this problem a new tool is proposed based on VHDL Parsing Expression Grammar (PEG). Functional Constraint Extraction (FCE) at Register Transfer Level approach is used in this new tool. This Functional Constraint Extraction (FCE) is used in ATPG process to generate pseudo functional scan test patterns which avoids ISE’s. The end result of this brief is an automatic tool that performs HDL parsing and analysis of legal state computation and functional constraint generation. This approach is also used to avoid the false error detection during RTL simulation.